A method of manufacturing a capacitor according to a prior art will be described briefly with reference to FIGS. 1 and 3.
An active region A and a field region B are defined by isolation technology. A field oxide film 2 is formed on a silicon substrate 1 in the field region B. A gate oxide film 14 of the transistor is formed on the silicon substrate 1 in the active region A. A first polysilicon layer 3, a first tungsten silicide layer 4 and a second polysilicon layer 5 with a high impurity concentration are sequentially formed on the field oxide film 2 and the gate oxide film 14. A dielectric film 6 with an ONO(Oxide-Nitride-Oxide) structure is formed on the second polysilicon layer 5. A third polysilicon layer 7 with a high impurity concentration and second tungsten silicide layer 8 are sequentially formed on the dielectric film 6. Then, the third polysilicon layer 7 with a high impurity concentration and the second tungsten silicide layer 8 are patterned by a first mask work and a first etching process, whereby a top plate of the capacitor consisting of the third polysilicon layer 7 and the second tungsten silicide layer 8 is formed at the top plate region E of the capacitor. During the first etching process, the dielectric film 6 and the second polisilicon layer 5 are patterned. Then, the first polysilicon layer 3 and the first tungsten silicide layer 4 are patterned by a second mask work and a second etching process, whereby the bottom plate consisting of the first polysilicon layer 3 and the first tungsten silicide 4 is formed at the bottom plate region D of the capacitor. Also the gate electrode consisting of the first polysilicon layer 3 and the first tungsten silicide layer 4 is formed on the silicon substrate 1 of a gate electrode region C. The bottom plate of the capacitor includes the patterned second polysilicon layer 5.
To complete the formation of the transistor at the active region A, a diffusion region 15 is formed by a source and drain impurity ion implantation process.
Then, after an interlayer insulation film 9 is formed on the entire structure including the transistor and the capacitor, using a metal contact process, a plurality of metal wires 11 are connected to the diffusion region 15 of the transistor and each of the top and bottom plates of the capacitor at a contact region F. The metal wires 11 are formed at the metal wire region G.
A method of manufacturing a capacitor according to another prior art will be described briefly with reference to FIGS. 2 and 3.
The capacitor shown in FIG. 2 has an insulation spacer 12 and a filament 13 formed at the bottom plate portion. As such, the detailed description for each element will be omitted and each of the numbers indicated in FIG. 2 shall correspond to the numbers indicated in FIG. 1 except for the "A" attached thereto.
According to the prior arts, the top plate of the capacitor is first formed and then the bottom plate of the capacitor and the gate electrode of the transistor are formed. The area of the bottom plate must be much larger than that of the top plate in consideration of a margin of metal contact process. As the areas of the top and bottom plates differ, their capacitance values are asymmetric. As a result, when the semiconductor device is used, erroneous input and output signals can be produced. Also, in case a filament is formed as in another conventional embodiment of the prior art, a short can occur between the top and bottom plates of the capacitor, thereby causing failure in the capacitor.